1. Technical Field
The embodiments of the invention generally relate to a semi-conductor element, in particular, to a memory structure which could avoid word line opening or linewidth necking.
2. Background
Memory cells are semiconductor elements used for storing information or data, and are widely applied to computers or electronic apparatus. Since the functions of micro processors have become stronger, demands for various types of memory have also been increased. According to different requirements of memory types, different structural designs of memory have been provided, such as a vertical-channel memory (VC memory) with a vertical channel structure, a floating-gate memory (FG memory) with a oxide recess structure, and a 3D memory with a thin film-stacked structure, etc.
In a general memory layout, a word line strides across an active region, that is, a device-concentrated region wherein a plurality of memory cells are disposed, which also could be called a memory cell region. Usually, in the front end process of semiconductor devices, the structural design of memory cells results in a larger step difference at the boundary of the conductive layer used to form word lines and the device-concentrated region. The step difference leads to a defocus phenomenon in a later lithography process for pattering a conductive layer, so that the word line formed in such process may have word line opening or necking issues. Therefore, the quality and efficiency of production get lower. With the miniaturization of semiconductor devices, an appropriate solution to the problem is required.